MOS (metal-oxide-semiconductor) transistor is one of the most important components in modern integrated circuits (ICs). The basic structure of a MOS transistor includes: a semiconductor substrate, a gate structure, a source region formed on one side of the gate structure, and a drain region formed on another side of the gate structure. In addition, the gate structure may further include a dielectric layer formed on the surface of the semiconductor substrate and a gate electrode formed on the surface of the dielectric layer.
According to existing fabrication methods for MOS transistors, at the beginning of the fabrication process, a dielectric layer is usually formed on a semiconductor substrate. A gate electrode layer may then be formed on the dielectric layer. Further, a gate structure may be formed by etching the dielectric layer and the gate electrode layer. Finally, a source region and a drain region may be formed respectively in the semiconductor substrate on the two opposite sides of the gate structure. The dielectric layer in such a MOS transistor is usually made of an oxide material such as SiO2.
With continuous increase of the integration degree of MOS transistors, the voltage and the current required for operating MOS transistors steadily decrease and the switching speed of the transistors also increases. As a consequence, substantial improvement on the semiconductor technology may be required. To this end, in the semiconductor industry, a method of using a high-k material to replace SiO2 for the fabrication of the dielectric layer has been developed in order to provide better isolation between the gate structure and other components of a MOS transistor and reduce current leakage. In the meantime, a metal material is also adopted to replace the traditionally used polycrystalline silicon for fabricating the gate electrode layer in order to be compatible with the high-k (k is greater than 3.9) material. For MOS transistors fabricated with a high-k dielectric layer and a metal gate layer, the leakage current may be further reduced and the gate driving capability may also be effectively improved.
However, a large number of interface states may exist at the interface between the high-k dielectric layer and the semiconductor substrate. During the fabrication process of the MOS transistor, such interface states may form unstable chemical bonds with hydrogen, thus may further affect the performance of the MOS transistor. In particular, severe negative bias temperature instability (NBTI) effect may exist in p-channel MOS (PMOS) transistors. Therefore, the performance and the reliability of PMOS transistors formed by existing methods may be poor.
The disclosed fabrication method and device structure in the present disclosure are directed to solve one or more problems set forth above and other problems in the art.